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W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
Features
* * * * * * * * * * * * JEDEC standard 144 pins, small-outline, dual in-line memory module (SODIMM) Two memory rows on this module (Double Bank Module) Utilizes 100 MHz SDRAM components Unbuffered SO-DIMM Auto Refresh and Self Refresh CAS latency: 2 and 3 Burst Length: 1, 2, 4, 8 and full page 4k refresh cycles/64ms Interface: LVTTL Serial Presence Detect with EEPROM Single 3.3V0.3V power supply PCB: height (1,062 mil) single sided component
Part Number
Module Part Number W9864AASA-10 W9864AASA10L Speed Grade PC66 CL=2, 3 PC66 CL=2, 3 Self-Refresh Current 8mA 1.8mA
General Description
The Winbond W9864AASA is a 8M x 64 Synchronous Dynamic RAM memory module. This module consists of eight pieces of W986416AH (4M x 16 bit) SDRAMs in 54-pin TSOP-II 400mil package, and a 2K EEPROM in 8-pin SOP package on a 144-pin 6-layer PCB. A 0.1 uF decoupling capacitor is used for each SDRAM. The W9864AASA is a Samll Out-line Dual In-line Memory Module for mounitng into 72-pin dual readout zigzag edge connector sockets. It is designed to operate in 3.3V, low-power memory systems.
Revision 0.9
1 OF 12
Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
Pin Assignment
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin 51 53 55 57 59 Front DQ14 DQ15 VSS NC NC Pin 52 54 56 58 60 Back DQ46 DQ47 VSS NC NC Pin 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Front DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **SDA VDD Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **SCL VDD
Voltage Key
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 CLK0 VDD RAS# WE# CS0# CS1# NC VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 CKE0 VDD CAS# CKE1 A12 *A13 CLK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52
* These pins are not used in this module. ** These pins should be NC in systems which do not support SPD.
FRONT 1 59 61 143
2
60
62 BACK
144
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
Pin Description
Pin CLKn CSn# CKEn A0~A11 BA0~BA1 RAS# CAS# WE# DQM0~7 DQ0~63 VDD VSS SCL SDA NC Name Clock Inputs Chip select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Input/Output Mask Data Input/Output Power (+3.3V) Ground Serial Clock Serial Data I/O No Connection Function Description System clock used to sample inputs on the rising edge of clock. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self-Refresh mode is entered. Multiplexed pins for row and column address. Row address: A0~A11. Column address: A0~A7. Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Command input. When sampled at the rising edge of the clock, RAS#, CAS# and WE# define the operation to be executed. Referred to RAS# Referred to RAS# The output buffer is placed at Hi-Z when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write data. Multiplexed pins for data output and input Power for input buffers and logic circuit inside SDRAM. Ground for input buffers and logic circuit inside SDRAM. Clock for serial presence detection Data line for serial presence detection No connection
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
BLOCK DIAGRAM
CS0 CS1 DQM0 DQ (7:0) U1 DQM1 DQ (15:8) U5 DQM5 DQ (47:40) DQM4 DQ (39:32) U3 U7
DQM2 DQ (23:16) U2 DQM3 DQ (31:24) U6
DQM6 DQ (55:48) U4 DQM7 DQ (63:56) U8
SERIAL PD SCL SA2 SA1 SA0 U9 SDA
CKE0 CKE1 RAS CAS WE A(11:0)
SDRAM U1~U 4 SDRAM U5~U8 SDRAM U1~U8 SDRAM U1~U8 SDRAM U1~U8 SDRAM U1~U8 SDRAM U1~U8
10R
VDD
SDRAM U1~U8
One 0.1uF per SDRAM device
BA(1:0)
CLK0
SDRAM U1~U4
10R
VSS
SDRAM U1~U8 CLK1 SDRAM U5~U8
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VIN, VOUT VDD TOPR TSTG
ITEM
Input, column Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current
RATING
-0.3~VCC+0.3 -0.3~4.6 0~70 -55~125 9 50
UNIT
V V C C W mA
NOTES
PD
IOUT
Note: Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70C )
SYMBOL VDD VIH VIL PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage MIN 3.0 2.0 -0.3 TYP 3.3 MAX 3.6 VCC+0.3 0.8 UNIT V V V NOTES
Note: VIH(max)=VDD +1.2V for pulse width < 5ns
VIL(min)=VSS -1.2V for pulse width < 5ns All voltages are referenced to VSS
CAPACITANCE (VCC=3.3V, Af = 1MHz, Ta=25C)
PIN
Address(A0~A11, BA0~BA1) RAS#, CAS#, WE# CKE0, CKE1 CLK0, CLK1 CS0#, CS1# DQM0~DQM7 DQ0~DQ63
SYMBOL
Cadd Ccmd CCKE CCLE CCS CDQM CIO
MIN
-
MAX
32 32 16 24 16 8 10
UNIT
pf pf pf pf pf pf pf
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
DC CHARACTERISTICS
(VCC = 3.3V 0.3V, Ta=0~70C)
SYMBOL ITEMS OPERATING CURRENT tCK=min, tRC=min Active Precharge command cycling without Burst operation STANDBY CURRENT tCK=min , CS#=VIH VIH/L=VIH(min)/VIL(max) Bank: inactive state STANDBY CURRENT CLK=VIL, CS#=VIH VIH/L=VIH(min)/VIL(max) BANK: inactive state -10 MIN MAX MIN 10L MAX UNIT NOTES
ICC1
1 bank operation
640
640
mA
1, 3
ICC2 ICC2P ICC2S ICC2PS ICC3 ICC3P ICC4 ICC5 ICC6
CKE=VIH CKE=VIL (Power Down mode) CKE=VIH CKE=VIL (Power Down mode)
400 24 40 16 480 64 960 720 16
400 mA 24 40 mA 16 480 64 960 720 3.6 mA mA mA mA mA 1, 3 1 1, 2, 3 1, 3 1
No OPERATING CURRENT CKE=VIH TCK=min0, CS#=VIH(min) BANK: active state (4 CKE=VIL (Power banks) Down mode) BURST OPERATING CURRENT TCK=min Read/Write command cycling AUTO REFRESH CURRENT TCK=min Auto Refresh command cycling SELF REFRESH CURRENT Self Refresh mode CKE=0.2V
Note: 1. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values
of tCK and tRC. 2 . These parameters depend on the output loading conditions. Specified values are obtained with output open. 3 . These values are measured under the following conditions Front (or back): Under the measuring conditions given on the data sheet Back (or front): In stand by (measured under the ICC2 conditions)
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
AC CHARACTERISTICS AND OPERATING CONDITION
( Vcc=3.3V0.3V, Ta=0 to 70C )
SYMBOL tRC trAS tRCD tCCD tRP tRRD tWR tCK tCH tCL tAC tOH tHZ** tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC PARAMETER Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/Write(b)Command Period Precharge to Active(b) Command Period Active(a) to Active(b) Command Period Write Recovery Time CL*=2 CL*=3 CLK Cycle Time CL*=2 CL*=3 CLK High Level CLK Low Level Access Time from CLK CL*=2 CL*=3 Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time - 10 MIN 90 60 30 1 30 20 15 10 15 10 3 3 MAX 100000 MIN 90 60 30 1 30 20 15 10 15 10 3 3 10L MAX 100000 UNIT ns cycle
1000 1000
1000 1000
9 8 3 3 0 0 0.5 3 1 3 1 3 1 3 1 20 10 10 10 3 3 0 0 0.5 3 1 3 1 3 1 3 1 20
9 8 10 10 10
ns
64
64
ms ns
Note: *CL=CAS Latency
** tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. Refer to the individual component
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
AC TESTING CONDITIONS
Output Timing Measurement Reference Level Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signal Input Reference Level 1.4V/1.4V See diagram B Below 2.4V/0.4V 2ns 1.4V
3.3V
1.4 V
1.2K
50 ohms
output 50pF 0.87K
output
Z = 50 ohms 50pF
AC TEST LOAD (A)
Note: Transition times are measured between VIH and VIL
AC TEST LOAD (B)
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.
Table 1: Truth Table
COMMAND Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect Auto-Refresh Self-Refresh Entry Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Data write/Output Enable Data Write/Output Disable Device state Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R.) Active Idle Active (5) Active Any (power down) Active Active
( note (1), (2))
CKEn-1 H H H H H H H H H H H H H L L H H H L L L H H CKEn X X X X X X X X X X X H L H H L L L H H H X X DQM X X X X X X X X X X X X X X X X X X X X X L H BA0, BA1 V V X V V V V V X X X X X X X X X X X X X X X A10 V L H L H L H V X X X X X X X X X X X X X X X A11, A9-0 V X X V V V V V X X X X X X X X X X X X X X X ___ CS L L L L L L L L L L H L L H L X H L X H L X X ___ ____ RAS CAS L L L H H H H L H H X L L X H X X H X X H X X H H H L L L L L H H X L L X H X X H X X H X X ___ WE H L L L L H H L H L X H H X X X X X X X X X X
Notes:
(1) V=Valid X=Don't care L=Low Level H=High Level (2) CKEn signal is input level when commands are provided. (3) These are state of bank designated by BA0, BA1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
Serial Presence Detect EEPROM
The Serial Presence Detect (SPD) function is implemented using a 2,408-bit EEPROM component. This nonvolatile storage device contains data for identifying the module type and various SDRAM organization and timing parameters. System read operations to the EEPROM device occur using the DIMM SCL(clock) and SDA (data) signals, together with SA(2:0) which provide the EEPROM Device Address.
SPD EEPROM DC OPERATING CONDITIONS
(Vcc=3.3V0.3V)
PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs OUTPUT LOW VOTAGE, lout=3 mA INPUT LEAKGE CURRENT, Vin=GND to Vcc OUTPUT LEAKAGE CURRENT, VOUT=GND to Vcc STANDBY CURRENT SCL=SDA Vcc -0.3V, All other inputs=GND or 3.3V +10% POWER SUPPLY CURRENT SCL clock frequency =100KHz SYMBOL VCC VIH VIL VOL ILI ILO ISB ICC MIN 3.0 VCCx.7 -0.3 MAX 3.6 VCC + .5 VCCx.3 0.4 1 1 10 1 UNIT V V V V uA uA uA mA NOTES
IOL=3mA
SPD AC OPERATING CONDITIONS
(Vcc=3.3V0.3V)
AC CHRARCTERICS SYMBOL SCL clock frequency fSCL Noise Suppression Time Constant at SCL, SDA Inputs tI SCL Low to SDA Data Out Valid tAA Time the bus must be free before a new transition can start tBUF Start Condition Hold Time tHD:STA Clock Low Period tLOW Clock High Period tHIGH Start Condition Setup Time tSU:STA Data in Hold Time tHD:DAT Data in Setup Time tSU:DAT SDA and SCL Rise time tR SDA and SCL Fall Time tF Stop Condition Setup Time tSU:STO Data Out Hold Time tDH Write Cycle Time tWR PARAMETER MIN MAX 100 100 3.5 UNIT KHz ns us us us us us us us ns us ns us ns ms NOTES
0.3 4.7 4.0 4.7 4.0 4.7 0 250
1 300 4.7 300 15
Note:
The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle the EEPROM bus interface circuits are disabled, SDA is allowed to remain high the bus level pull-up resistor, and the device does not respond to its slave address.
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
CONTENTS OF EEPROM (SPD Version 1.2)
BYTE NUMBER
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 64-71 72 73-90 91-92 93-94 95-98 99-125 126 127 128+
FUNCTION DESCRIBED
Defines # bytes written into serial memory at module manufacturer Total # bytes of SPD memory device Fundamental memory type (FPM, EDO, SDRAM..) # Row Addresses on this assembly # Column Addresses on this assembly # Module Rows on this assembly Data Width of this assembly... Data Width continuation Voltage interface standard of this assembly SDRAM Cycle time @CAS latency of 3 SDRAM Access time form clock @CAS latency of 3 DIMM Configuration type (Non-parity, Parity ECC) Refresh Rate/Type SDRAM width, Primary DRAM Error Checking SDRAM data width Minimum Clock Delay, Back Random Column Addresses Burst Lengths supported #Bank on Each SDRAM device CAS# Latencies Supported CS# Latency Write Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM cycle time @CAS latency of 2 SDRAM access time form clock @CAS latency of 2 SDRAM cycle time @CAS latency of 1 SDRAM access time from clock @CAS latency of 1 Precharge to active command period (tRP) Active to Active command period (tRRD) Active to Read/Write command delay time(tRCD) Minimum Active to precharge period (tRAS) Density of each Row on Module Command and Address signal input setup time Command and Address signal input hold time Data signal input setup time Data signal input hold time Superset Information(may be used in future) SPD Revision Checksum for Bytes 0-62 Manufacturers code Manufacturing location Manufacturer's Part Number Revision Code Manufacturing Date Assembly Serial Number Manufacturer Specific Data Intel specification for frequency CAS latency for 66MHz Unused storage locations
FUNCTION SUPPORTED -10/10L
128 bytes 256 bytes (2K-bit) SDRAM 12 8 2 row 64 bits LVTTL 10ns 8ns Non parity 15.625 us, support self refresh X16 None TCCD=1 CLK 1, 2, 4, 8 & full page 4 banks 2&3 0 CLK 0 CLK Non-buffered Non -registered & redundant addressing +/-10% voltage tolerance, Burst Read, Single bit Write, precharge all, auto precharge 15ns 9ns 30ns 20ns 30ns 60ns 2 row of 32MB 3ns 1ns 3ns 1ns Current release Intel spd 1.2 -
HEX VALUE -10/10L
80h 08h 04h 0Ch 08h 02h 40h 00h 01h A0h 80h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh F0h 90h 00h 00h 1Eh 14h 1Eh 3Ch 08h 30h 10h 30h 10h 00h 12h E3h MFG Dep MFG Dep MFG Dep MFG Dep MFG Dep MFG Dep MFG Dep 66h 06h FFh
66MHz CAS latency of both 2 & 3
Revision 0.9
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Publication Release Date:98/05/18
W9864AASA 64MB (8M x 64) SDRAM SO-DIMM MODULE
PACKGE DIMENSIONS
Units:Inches
2.660
0.007
2.500 2-R 0.079 1.062 0.007 0.160 Max 0.039
0.240
0.160
1
143
0.130
0.910 A
1.290 0.083 0.100 B 2-R 0.07
0.024 0.001 0.0039 0.010 Max
0.100 Min
0.16
0.060 0.0039 Detail A
0.030 TYP Detail B 0.005
Tolerance : 0.005 unless otherwise specified The used device is 4Mx16 SDRAM,TSOP
Revision 0.9
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Publication Release Date:98/05/18
0.100
0.790

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